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Title of Paper |
Authors |
170601 |
COMPUTER AIDED DESIGN AND ANALYSIS OF AN G+6 FIVE APARTMENT RESIDENTIAL COMPLEX USING STAAD.PRO
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G MADHU KUMAR,Mr. P.HANMANDLU
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170602
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DESIGN OF FIXTURE TO OPTIMISE PROCESS PLAN OF AEROSPACE COMPONENT
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DURGA BHAVANI,G. VENKATESH
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170603 |
OPTIMIZATION IN MANUFACTURING PROCESS OF ARTILLERY FUZE BY USING DESIGNED FIXTURE
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MIDIDODDI JYOTHI,VEMURI VENKATA PHANI BABU
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170604 |
DESIGN, ANALYSIS AND MANUFACTURING OF PRESSURE VESSELS
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Y.VASUDHAR,L B BHARATH RAJU
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170605 |
SECURITY, CONTROL AND ACCESS ON IOT AND ITS THINGS
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V. SRIKANTH
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170606 |
DESIGNING AND MANUFACTURING OF TOOTH WHEEL USED IN METRO TRAINS-
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B.V.M.D.N.S PAVAN, SINGHIE .G
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170607 |
FALL ALARM AND INACTIVITY DETECTION SYSTEM DESIGN AND IMPLEMENTATION ON RASPBERRY PI
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KAMA MOUNIKA, K.SONI
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170608 |
THE EFFECTIVE GENUINE SIGNIFICANT EXCHANGE PROTOCAL FOR PNFS
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GODDE. VARAMMA,GURRAPU.NEELIMA
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170609 |
AN ADAPTIVE CURRENT SOURCE INVERTER FOR HARMONIC ENERGY COHORTS
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A DEVI SHALINI,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
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170610 |
A COMPENSATION TECHNIQUES OF RAILWAY POWER CONDITIONER FOR RAILWAY POWER SYSTEM
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ANKALA HAREESH KUMAR,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
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170611 |
ANALYSIS OF DIFFERENT TOPOLOGIES FOR ACTIV POWER FACTOR CORRECTION IN DC – DC CONVERTERS
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GUNTAKANDLA VIKRAM,M RAVINDAR,RAMAVATH SHANKAR NAIK
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170612 |
A DESIGN OF ULTRA CAPACITOR FOR IMPROVING POWER QUALITY OF DISTRIBUTION GRID BY AN INTEGRATED DYNAMIC VOLTAGE RESTORER
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M NAGARAJU,RAMAVATH SHANKAR NAIK
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170613 |
ENHANCEMENT OF POWER QUALITY IMPROVEMENT GRID CONNECTED DUAL VOLTAGE SOURCE INVERTER
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MANTHENA RAGHUVARAN,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
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170614 |
Fault current and overvoltage limitation in a distribution network with distributed Generation units through superconducting fault current limiter
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DESHAVENI DEEPAK, M RAVINDAR, RAMAVATH SHANKAR NAIK
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170615 |
GRID VOLTAGE REGULATION BY USING PV BASED DUAL TOPOLOGY OF THE UNIFIED POWER QUALITY CONDITIONER(IUPQC)
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M PADMAJA, RAMAVATH SHANKAR NAIK
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170616 |
IMPROVEMENT OF POWER QUALITY BY USING A ROBUST HYBRID SERIES ACTIVE POWER FILTER
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POLAGONI SHIVAJI,M RAVINDAR,RAMAVATH SHANKAR NAIK
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170617 |
UNDER DISTORTED GRID VOLTAGE DIRECT POWER CONTROL OF DOUBLY FED INDUCTION GENERATOR
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SHAGANTI PRAVEEN,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
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170618 |
TRACKING THE MAXIMUM POWER POINT WITH ARTIFICIAL NEURAL NETWORK
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CHINTHAMOLA VISHNUVARDHAN REDDY,RAMAVATH SHANKAR NAIK
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170619 |
GRID SYNCHRONIZATION METHOD FOR THREE PHASE THREE WIRE NETWORKS UNDER GRID FAULT CONDITION
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NELAGUDUTI UPENDAR,RAMAVATH SHANKAR NAIK
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170620 |
ENHANCEMENT OF POWER QUALITY USING SELF SUPPORTED DVR
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KALYADAPU RAJASHEKAR,RAMAVATH SHANKAR NAIK
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170621 |
AN EFICIENT CONSTRUCTION CALLED DEYPOS, TO ACHIEVE DYNAMIC POS AND SECURE CROSS-USER DEDUPLICATION
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RAGHUVEER REDDY
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170622 |
REDUCTION OF STATIC POWER BY USING BIASING AND BODY BIASING TECHNIQUES
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B MOUNIKA,K BHAVANI
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170623 |
A FRAMEWORK TO DETECT AND CORRECT ERRORS IN CIRCUITS
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B SANDHYA,AYESHA BEGUM
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170624 |
POST OPTIMIZATION OF A CLOCK TREE FOR VIGOR GIVE NOISE REDUCTION
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E Saresh Kumar,M SreeChandana
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170625 |
POWER EFFICIENT PARALLEL CHIEN SEARCH ARCHITECTURE USING A TWO STEP APPROACH IN RS CODES
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M ANJANEYULU,K BHAVANI
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170626 |
ANALYSIS OF DATA HIDING TECHNIQUES IN ENCRYPTED IMAGES - A SURVEY
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G MOUNIKA,G SATHYA PRABHA
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170627 |
ADOPTING NR4SD+ SCHEME INTO DSP
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R RAMYAM,M SREECHANDANA
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170628 |
A NOVEL FPGA DESIGN WITH HYBRID LUT/MULTIPLEXER ARCHITECTURE
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A SHANKAR NAYAK,P V VARAPRASAD RAO
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170629 |
DESIGNING A LESS ENERGY AND LESS-SIZE SHIFT REGISTER FOR VLSI CIRCUIT USING PULSED HANDLES
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T SARASWATHI,P V VARAPRASAD RAO
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170630 |
Activity and Behavior Analytics of Big Data Hadoop Framework by Using the ML tensor sketch
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Ram Narayan Dash
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